1. Field of the Invention
The present invention relates to a three-dimensional, non-volatile memory structure of memory cells organized as NOR-type memory strings. More particularly, the present invention relates to data retrieval from a structure of such memory cells in which each memory cell is connected between a directly accessible drain electrode and a floating—but not directly accessible—source electrode.
1. Discussion of the Related Art
Non-volatile memory cells are often connected either serially (NAND) or in parallel (NOR) between two externally accessible electrical nodes (“electrodes”). In contrast to dynamic random-access memory (DRAM) cells, non-volatile memory cells retain their stored information after an access for data retrieval, or over a period during which power is removed. In a typical non-volatile memory cell, data is stored in an isolated charge-trapping layer in the form of injected electric charge that is created by, for example, Fowler-Nordheim tunneling. The stored information is typically retrieved using a non-destructive method that is based on either a measurable current flow, or a measurable change in voltage level. The result of the measurement is typically provided in the form of digital information by a “sense amplifier.” The current flow method is called “current-sensing,” while the voltage change method is called “voltage-sensing.” From this perspective, a sense amplifier is a digital ammeter, when used for current sensing, or a digital voltmeter, when used for voltage-sensing.
FIG. 1A shows a sense amplifier circuit, described in U.S. Pat. No. 7,046,568, that is capable of both current-sensing and voltage-sensing. FIG. 1B illustrates a simplified sense amplifier circuit, based on the sense amplifier circuit of FIG. 1A, operating under the current-sensing mode. As shown in FIGS. 1A and 1B, memory cell 100 is connected between bit line (BL) 101, which is heavily loaded with parasitic capacitance (represented by capacitor 102 of FIG. 1B), and the ground reference. NMOS transistors 103 and 104 are connected in a cascode configuration to bias memory cell 100 to a time-independent drain voltage, thereby keeping the current in memory cell 100 constant, independent of the potential at node 106 (signal SEN). FIG. 1C shows voltage waveforms for various signals in the current-sensing operation of FIG. 1B. As shown in FIGS. 1B and 1C, node 106 is initialized to power supply voltage VDD by PMOS initialization transistor 105, so that level-sensitive PMOS transistor 110 is non-conducting, and bit line 101 is held at voltage BLC−VT, where voltage BLC is the voltage at the gate electrode of NMOS transistor 103 and VT is the threshold voltage of NMOS transistor 103. Capacitor 107—which may be a dedicated capacitor (i.e., an expressly provided capacitor, not a parasitic capacitor) with a smaller capacitance relative to parasitic bit line capacitor 102—is connected between node 106 and power supply voltage VDD. At time T1, initialization transistor 105 is turned OFF and memory cell 100—depending upon its conductive state—may or may not discharge capacitor 107. If memory cell 100 is not conductive, node 106 does not lose any charge and remains at its initial voltage VDD, so that PMOS transistor 110 is non-conducting. In this case, output electrode 111 of one of the coupled inverters remains at ground level. However, if memory cell 100 is conductive, the voltage on node 106 decreases. At time T2, when the voltage at node 106 decreases below “trip point” (TP) level 117, PMOS transistor 110 becomes conducting, driving output electrode 111 to supply voltage VDD.
Capacitor 107 performs two roles—i.e., as a noise filter and as a cell current evaluation device (through time integration). A constant current in the memory cell discharges capacitor 107 linearly (over time) towards TP level 117. As illustrated in FIG. 1C, different cell currents result in the voltage of node 106 having different slopes 113 and 114, with the steeper slope—indicated by waveform 114—corresponding to a higher discharge current. The voltage at output electrode 111 changes logic state, as illustrated by waveforms 115 and 116 (corresponding to slopes 113 and 114, respectively), when the voltage on node 106 crosses TP level 117. TP level 117 corresponds to the threshold voltage of PMOS transistor 110.
In FIG. 1B, additional transistor 108 has voltage BLX at its gate electrode, which is higher than voltage BLC at NMOS transistor 103, and supply voltage VDD at its drain electrode. Transistor 108 maintains the voltage at the drain electrode of transistor 103. This is because, as the voltage at node 106 decreases, the drain electrode of transistor 103 is held at voltage BLX-VT, which is higher than voltage BLC−VT at bit line 191, thereby ensuring that the voltage at bit line BL 101 remains constant at BLC−VT. Discharge time window 118, spanning the time period between T1 and T4, is calibrated in advance of the current-sensing operation, so as to provide discharge linearity at node 106 between supply voltage VDD and TP level 117. Below TP level 117, linearity may be lost, due to the overall circuit response. The circuit response includes transistor 110 becoming conducting and the voltage at the drain electrode of transistor 103 being held at BLX-VT without affecting accuracy. This operation of FIGS. 1B and 1C illustrates merely one type of current sensing operations. Alternatively, the cell current can also be assessed by mirroring the current and comparing it to a known reference.
FIG. 1D illustrates a simplified sense amplifier circuit, based on the sense amplifier circuit of FIG. 1A, operating under voltage-sensing mode. FIG. 1E shows voltage waveforms for various signals in the current-sensing operation of FIG. 1D. As shown in FIG. 1D, with its gate electrode at voltage BLC1, transistors 103 pre-charges bit line 101 (a capacitive node, as indicated by capacitor 102) from ground to voltage BLC1−VT (as illustrated by waveform 119 in FIG. 1E). The voltage at the gate electrode of transistor 103 is then lowered to voltage BLC2 value (indicated by waveform 120), thereby disconnecting bit line 101 from node 106. At time T1, a read voltage is applied to memory cell 100. Depending on its encoded state, activating memory cell 100 may or may not discharge bit line 101. The rate of discharge at bit line 101 may be significantly lower (e.g., orders of magnitude) relative to the “current-sensing” operations above, as capacitor 102 could be orders of magnitudes greater than capacitor 107 discussed above. Unlike current-sensing, the voltage-sensing operation does not require a dedicated capacitor 107. As shown in FIG. 1E, when the voltage at bit line 101 decreases below BLC2−VT (i.e., voltage level 120), node 106 is immediately pulled down (indicated in FIG. 1E by reference numeral 121). Eventually, bit line 101 discharges to ground. A major disadvantage of the voltage-sensing method is that it is time-consuming.
Neither the current-sensing method nor the voltage-sensing method can be used when the source electrode of memory cell 100 is not grounded, as memory cell 100 would not be able to act as an active pull-down to ground. There is no current flow to ground that can coerce a capacitive input terminal of a sense amplifier to cross a discrimination point through an intermediate circuit.